This invention relates to electronic adder circuits and more particularly to an improved chain-type ripple-carry generating circuit used to propagate carry signals in parallel, binary adders.
Chain-type ripple-carry generating circuits having a plurality of cascaded stages each using a transmission gate for controlling the propagation of a carry signal through the stage are well known for having the advantages of fast carry propagation, simple circuit topology and compact layout in an integrated circuit. Typically, each stage of a chain-type carry circuit has an input terminal for receiving an input carry signal, an output terminal for providing an output carry signal, a transmission gate having its conduction path connected in series between the input and output terminals, a clocked load transistor having its conduction channel connected between the output terminal and a VDD supply terminal, and a carry-out logic network connected to the output terminal and responsive to an addend and an augend signal for providing an appropriate output carry signal.
Because each stage of the carry circuit introduces a series resistance and a parallel capacitance to the carry propagation path, the propagation delay of a carry signal through a carry circuit having a plurality of stages increases rapidly with the number of such stages. Furthermore, since carry propgation in a dynamic carry circuit occurs only during a fixed active interval, a carry signal after propagating through a long section of the carry circuit may be so delayed that its amplitude does not reach its final logic level before the end of active interval and accordingly appears attenuated. Therefore, an excessively long carry signal propagation delay in a dynamic carry circuit causes the problem of carry signal attenuation which imposes limitations on the minimum active interval of such circuits and the maximum number of stages which may be included in such circuits.
One prior art solution to the carry signal attenuation problem in chain-type carry circuits is to divide a long carry circuit into short sections and to interpose a buffer amplifier between these sections for restoring the full logic level of the carry signal after each section. However, this solution is deficient in that each non-inverting buffer amplifier adds approximately two gate delays to the carry signal propagation time through the carry circuit, and the buffer amplifiers themselves become a major source of carry signal propagation delay. Moreover, the addition of buffer amplifiers in a carry circuit increases its layout area when used in an integrated circuit and, consequently, increases the manufacturing cost of such an integrated circuit. Therefore, a need clearly exists for a solution to the carry signal attenuation problem in chain-type ripple-carry generating circuits which overcomes the deficiencies of the prior art by permitting shorter carry signal propagation delay and more compact layout when used in an integrated circuit.